High-speed synchronous systems generally require a tightly controlled clock timing allowance for high performance operation. With source-synchronous interfaces, data and clock transport from a transmitter to a receiver, and the receiver interface employs the clock to latch the accompanying data. The device that transmits data also generates a data strobe signal that travels toward the receiving device along with the data signals. Such source-synchronous signaling eliminates problems associated with common clock systems such as propagation delay, clock skew, etc., thereby increasing the maximum operating frequency.
Source synchronous memory interfaces such as, for example, DDR (Double-Data-Rate) and source synchronous NAND Flash interfaces require a quarter cycle delay shifting of the read output DQS (Data Queue Strobe) coming from the memory device in order to robustly sample a read output data queue (DQ) within a PHY (Physical Layer). Accurate sampling of the read output data by the read output data strobe may require four linearly programmable delays for independently delaying the rising and falling edges of the read output data strobe and independently sampling a read output data byte into an upper and lower nibble to minimize skew effects. As frequency of operation decreases, the quarter-cycle delay increases and consequently the area overhead of four delays cells becomes a large percentage of the overall PHY area. Hence a solution is required to delay the read DQS from the flash device by a quarter cycle of its period in order to correctly sample the read data, DQ memory over a wide range of clock frequencies without the large area impact.
Conventionally, multiple fine delays are employed for achieving the optimum delay size. Such fine delays require large delay cells to achieve both the bulk delay and the fine granularity. Additionally, the fine delay must be pre-constructed utilizing either discrete gates or many simple standard cells such as, for example, NAND gates, which can be time consuming to construct such a delay that can maintain linearity (uniform delay steps) across its entire range. Furthermore, prior art methods only address PVT (Process, Voltage, Temperature) compensation of the fine delays or of a standalone coarse plus fine delay that combine to be a single linearly incrementing delay. A solution is required to address the PVT compensation of a standalone coarse plus fine delay that are not required to combine to be a single linearly incrementing delay.
Based on the foregoing, it is believed that a need exists for an improved non-linear common coarse delay system and method for delaying a data strobe to preserve fine delay accuracy and to compensate PVT variation effect. A need also exists for an improved method for determining a correct coarse and fine delay size based on frequency and expected PVT variation, as described in greater detail herein.